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What is the difference between the Intel 430HX PCIset and the Intel 430TX PCIset?
The Intel 430HX PCIset is a cost-effective solution for Pentium® processor-based systems with data integrity and reliability. It is designed for business desktops with ECC/parity. It supports more memory than any other Pentium processor chipsets (cacheability 512MB, max memory size 512MB). It is the only chipset in the Pentium processor family that supports dual processing.
The Intel 430TX PCIset delivers a better Pentium processor with MMX® technology-based multimedia and communication platform for home and small business use. It supports SDRAM and uses the PIIX4E southbridge, which supports Ultra DMA. It also contains a power management system, which allows bus signal voltage of either 5V or 3.3V. This power management feature allows the Intel 430TX PCIset to be incorporated into mobile applications.
How do I disable the L2 cache on an Intel 430HX PCIset design?
For power management, some designers may want to disable the cache from the Intel 430HX PCIset. Current documentation does not describe disabling cache or related chip select status.
To disable the L2 cache from the Intel 430HX PCIset, clear the following bits:
SCS (Cache Control Register, Bits[7:6]: Secondary Cache Size) = 00
FLCE(Cache Control Register, Bit 0: First Level Cache Enable) = 0
ECE (Cache Control Register, Bit 2: Extended Cacheability Enable) = 0
SCFMI (Cache Control Register, Bit 1: Secondary Cache Force Miss or Invalidate) = 0
See the Intel 430HX PCIset datasheet for further description of these bits.
If chip selects are asserted, the SRAM device would be selected and the power down state would be exited. The chip select lines will still be active even when L2 is turned off. Therefore, this may not work well with the power down mode on the SRAMs for a desktop design.
During a passive release, is CPU-PCI write posting disabled?
Posting of CPU to PCI writes is disabled from the time the passive release is initiated (toggling of PHLD#) until the active release is generated by the PIIX3 (holding PHLD# deasserted for at least 2 clock cycles). This active release indicates the end of the ISA transfer. This disabling is necessary to prevent deadlock scenarios.
Can the Intel 430HX PCIset handle more memory than it can cache? How much memory is cacheable by the chipset?
The Intel 430HX PCIset can cache up to 512 MB, while the Intel 430TX PCIset can cache 64 MB of memory. Each of these chipsets can handle a system with as much memory as the chipset's maximum memory size, but they will perform optimally when all of the memory is cached. For this reason performance may slow slightly when a system operates with more memory than its chipset can cache.
Does the Intel 430HX PCIset support read-modify-write transactions from PCI to DRAM?
If a PCI master locks DRAM, the PCI arbiter considers the arbitration "frozen" on the PCI master. In this state, AHOLD will remain asserted on the CPU bus so the CPU will not be allowed to start any cycles. However, it will be allowed to snoop write-backs. Therefore, read-modify-write transactions from PCI to DRAM are supported by the Intel 430HX PCIset.
What is the PIIX3 Controller?
The PIIX Controller is the south bridge component of a computing platform. It is a multi-function PCI to ISA/EIO Bridge that incorporates a USB controller, IDE Interface, DMA Controller, Real-Time Clock, Power Management, and the System Management Bus (SMBus). The PIIX3 is only supported on a 430HX PCIset based platform.
Why is the ISA MASTER# signal not implemented on the PIIX3?
The PIIX3 supports ISA master initiated memory cycles to PCI and ISA master-initiated cycles to the internal PIIX3 ISA-compatible registers. PIIX3 will detect an ISA Master access when it asserts DACK# for a compatible DMA channel that is programmed in cascade mode (as all ISA bus masters DMA channels must be). In other words, if a device that is programmed for cascade mode DMA transactions asserts its DRQ, the PIIX3 will assume that it is an ISA Master. Therefore, the ISA MASTER# signal does not need to be implemented.
In a system with two hard drives (one on each connector), can a seek request be sent to one drive and before this request completes, a second seek request be sent to the other drive?
If the drives are operating in PIO mode, the IDE controller must wait for the requested data to complete its transfer before accessing another drive. In bus master mode, after an acknowledge signal is received from the original device, the IDE controller can access another device on another connector while the first device is still accessing data.
Does the PIIX3 support USB?
Earlier versions of the PIIX3 had issues supporting USB. Only the B-0 stepping of the PIIX3 can properly support USB. B-0 step PIIX3 devices have an S-Spec of U093. Additional S-Spec data is available within the Intel 82371SB (PIIX3) PCIset Specification Update.
There may also be compatibility issues. The PIIX3 only supports USB Specification 1.0. The majority of USB devices today are USB 1.1 compatible, with some being USB 2.0 enabled. Because the specification change from USB 1.0 to USB 1.1 involved both hardware and software upgrades, there is no way for the PIIX3 to support USB 1.1. Contact the USB device manufacturer to determine whether or not the device is USB 1.0 compliant. Additional information is available from the Intel USB web site.
If the PIIX3 is implemented on a non-USB system, how is this feature disabled?
In order to disable USB, the following steps must be taken:
1. Pin 130 (Vcc3) should connect to a 3.3V or 5V power supply.
2. Pin 146 (USBCLK) should connect to ground.
3. Pins 142-145 (USB port pins) should each be terminated with a 15K pull down resistor. |
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Intel® 430HX PCIset