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Does the Intel 430TX PCIset chipset support dual processors?
No. The Intel 430TX PCIset is only capable of operating in a uni-processor environment.
Does the Intel 430TX PCIset support single and double cycle deselect SRAMs?
Yes, both the Intel 430HX and Intel 430TX PCIsets are capable of handling both single cycle and double cycle deselect SRAMs. In a single-bank solution, it doesn't matter which type you have in the system since there is never a deselecting of one bank to switch to another. As a result, 3-1-1-1,1-1-1-1 timings are possible with both types.
In a dual bank configuration, where 256KB banks are toggled via the A18 pin, it is possible to cross the bank boundary on an L1 cache line fill. If this occurs, then A18 toggles and the first bank is deselected while the second bank is selected. If the banks consist of single cycle deselect SRAM, then a wait state MUST be inserted before the latching of the second burst address (toggling A18) causing 3-1-1-1,2-1-1-1 timings. This is handled internally by the north bridge when bits 5:4 in the Cache Control register are both set to '1' to indicate dual cache configuration.
If double cycle deselect SRAMs are implemented in a dual bank configuration, then 3-1-1-1,1-1-1-1 timings are still possible since the wait state is not necessary. This can be achieved by "fooling" the cache controller into thinking that only one bank exists (via the Cache Control Register). If double cycle deselect SRAMs are used in a system where the cache control register is configured for two banks, then 3-1-1-1, 2-1-1-1 timings will result.
How is DRAM refresh performed during Suspend mode?
At the onset of suspend mode, the MTXC samples the SUS_STAT# pin active. This indicates to the north bridge that PCLK and HCLK will become invalid in as little as 32us. However, to maintain data integrity in the DRAM, refresh must continue. Thus, the MTXC is forced to use an alternate clock source (SUSCLK) for refresh timings. When the system resumes (comes out of power management), the HCLK will start. After reset, software sets the NREF (Normal Refresh Enable) bit in the MCTL register, switching the MTXC from suspend refresh to normal refresh (SUSCLK to HCLK). The entire MTXC, however, does not come out of suspend until SUS_STAT is de-asserted.
How are back-to-back burst accesses between a single bank and a two-bank SRAM cache solution performed when using an Intel 430TX PCIset?
To implement a two-bank solution in cache when performing back-to-back burst accesses, it is necessary to incur a one-clock cycle delay over a single bank solution. This ensures that one bank does not power-down before all data is driven out. For example, if using two banks of cache, when the seam is crossed from bank one to bank two, the J HA18 line (that feeds into CE2 or CE2# of the SRAM) will toggle. During this time, bank one valid data is still being driven out of the SRAM while the J HA18 line changes, and ADSP# on the SRAM (ADSC from the host) is active. The bank one SRAM interprets this disabling of chip enable as a request to enter a low power mode, and the current data will be lost.
To prevent losing the current data, the CCS# pin from the chipset (attached to CE# on the SRAM) must be negated. When negated, the ADSP# on the SRAM is ignored and the device will wait to sample the new address until the CADS# signal from the chipset (ADSC# on the SRAM) is active. At this time, the current transfer is complete and no data is lost. Therefore, a 2-bank solution performs back-to-back burst accesses at 3-1-1-1-2-1-1-1, and a 1-bank solution accesses at 3-1-1-1-1-1-1-1.
Does the 430TX support AGP?
Chipsets that do support AGP, such as the 440BX, has a secondary internal arbiter within the chipset, exclusive to AGP. This second arbiter works directly between the graphics device and memory, improving performance. Without the arbiter, AGP cannot be used, since it cannot operate fast enough. Chipsets such as the 430TX do not have the additional pins required to connect a separate AGP controller for the chipset. There are AGP connectors for the PCI bus, which provide AGP support. These connectors are available through Third Party Vendors, not from Intel.
What is a PIIX4E?
The PIIX4E is the south bridge component of a computing platform. It is a multi-function PCI to ISA/EIO Bridge that incorporates a USB controller, IDE Interface, DMA Controller, Real-Time Clock, Power Management, and the System Management Bus (SMBus). The PIIX4E can be supported on either a 430TX or 440BX chipset based platform.
What is the difference between the PIIX4 (82371AB) and the PIIX4E (82371EB)?
The PIIX4E is the replacement for the end of lifed PIIX4. The PIIX4E is form, fit, and functionally identical to the PIIX4, but it has added Advanced Configuration and Power Interface (APCI) power management capability. The PIIX4E Specification Update can be downloaded from the developer's web site.
Does the 430TX and PIIX4E support Ultra ATA/66?
The Intel 430TX chipset can only support hard drives up to ATA33. Most Ultra ATA/66 hard drives are backwards compatible for ATA33. You will need to verify with your hard drive manufacturer if your Ultra ATA/66 drive supports ATA33, or if additional drivers are required to run at ATA33.
How does the Subtractive Decode feature of the PIIX4E work?
The greatest misunderstanding of the PIIX4E's Subtractive Decode feature is that it will capture ALL unclaimed PCI cycles and forward them to the ISA bus. This is not true. The PIIX4E will only forward those cycles that fall within the ISA range of memory. The ISA bus only supports a total of 24 address lines, limiting memory addresses to 00FFFFFFh, or 16MB. Memory address 01000000h or above are only supported by the PCI bus. The PIIX4E will never Subtractive Decode an address above 16MB.
How do I use the PIIX4E's PC/PCI DMA function?
PC/PCI DMA will support most I/O devices on the PCI bus via the REQ#/GNT# signals. This I/O device needs to arbitrate for communication with the PIIX4E's DMA controller on the PCI bus, similar to a PCI Bus Master. To accomplish this, PC/PCI serial protocol must be followed. The requesting agent (I/O device) has to support the proper channel encoding, while the GNT# signal needs to decode the granted information. This is required for proper device synchronization between the I/O device and the PIIX4E, even if it is the only device using a PC/PCI DMA channel.
DMA 0-3 are 8-bit count-by-byte channels while DMA 5-7 are 16-bit count-by-word channels. The channel can be configured for any mode, except cascading. Additional information is available in chapter 8.5 of the PIIX4E's datasheet.
If the PIIX4E is implemented on a non-USB system, how is this feature disabled?
In order to disable USB, the following steps must be taken:
1. Ball K5 (VccUSB) should connect to a 3.3V power supply.
2. Ball L3 (CLK48) should connect directly to ground.
3. Ball G2, H3, F1, H2 (USB port pins) should each be terminated with a 15K-ohm pull down resistor.
4. Ball J1, J2 (OC[1:0]#) should each be terminated with a 10K-ohm pull up resistor to 3.3V.
How can Flash be implemented in an Embedded System?
For implementing flash memory on the ISA bus, please refer to AP-664 Designing Intel StrataFlash® Memory into Intel® Architecture.
For implementing flash memory on the PCI bus, please refer to AP-758 Flash Memory PCI Add-In Card for Embedded Systems. The Flash Memory PCI Add-In Card for Embedded Systems Schematics and Software Files are also available. |
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Intel® 430TX PCIset