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What kind of SDRAM clock buffer should I use with the 440BX?
Zero delay clock buffers have internal PLLs which cause contention with the PLL internal to the 440BX. This contention can be observed in the form of jitter on the 440BX DCLKO and DCLKWR signals. As another observable symptom the system will lockup after the processor attempts to fetch the first 8 bytes of BIOS. The customer should use SDRAM clock buffers that do not have an internal PLL.
Are 256Mbit SDRAM's supported?
The 82443BX does not support 256Mbit technology SDRAM.
128Mbit technology SDRAM using 16MX8 devices has been tested in the Intel® 82440BX System Validation (SV) platform using the 82443BX C-1 stepping. This SDRAM memory configuration was double-sided. Each SDRAM DIMM module therefore contained a total of 256MB of memory. A total of four DIMM modules were available for testing. For further information please see page 25 of the specification update.
There were no detection or sizing problems with this SDRAM memory array using the 82440BX SV board and 82440BX SV BIOS. The 82440BX AGPset supports the use of 128Mbit technology SDRAM memory using the 82443BX C-1 stepping as described in this paragraph.
Where can BGA packaging information be found?
The 440BX is manufactured in a 492-pin PBGA packaging. Details on the packaging can be found in the
440BX datasheet. Further requirements for the 492 PBGA packaging can be found in Chapter 14 (PDF 795KB) of the Intel Packaging Handbook.
Can the Intel® Pentium® III processor in FC-PGA packaging be used in a dual processing configuration with the 440BX?
The 440BX chipset does not support a dual FC-PGA design due to IO-APIC issues. Intel provides no documentation or support for designing a dual FC-PGA system. Customers wanting to design a dual-processor FC-PGA system will need to perform their own validation.
How does the PIIX4E perform Subtractive Decode?
The greatest misunderstanding of the PIIX4E's Subtractive Decode feature is that it will capture ALL unclaimed PCI cycles and forward them to the ISA bus. This is not true. The PIIX4E will only forward those cycles that fall within the ISA range of memory. The ISA bus only supports a total of 24 address lines, limiting memory addresses to 00FFFFFFh, or 16MB. Memory address 01000000h or above are only supported by the PCI bus. The PIIX4E will never Subtractive Decode an address above 16MB.
How does the PIIX4E perform PC/PCI DMA?
PC/PCI DMA will support most I/O devices on the PCI bus via the REQ#/GNT# signals. This I/O device needs to arbitrate for communication with the PIIX4E's DMA controller on the PCI bus, similar to a PCI Bus Master. To accomplish this, PC/PCI serial protocol must be followed. The requesting agent (I/O device) has to support the proper channel encoding, while the GNT# signal needs to decode the granted information. This is required for proper device synchronization between the I/O device and the PIIX4E, even if it is the only device using a PC/PCI DMA channel.
DMA 0-3 are 8-bit count-by-byte channels while DMA 5-7 are 16-bit count-by-word channels. The channel can be configured for any mode, except cascading. Additional information is available in chapter 8.5 of the
PIIX4E datasheet.
If the PIIX4E is implemented on a non-USB system, how is this feature disabled?
In order to disable USB, the following steps must be taken:
1. Ball K5 (VccUSB) should connect to a 3.3V power supply.
2. Ball L3 (CLK48) should connect directly to ground.
3. Ball G2, H3, F1, H2 (USB port pins) should each be terminated with a 15K-ohm pull down resistor.
4. Ball J1, J2 (OC[1:0]#) should each be terminated with a 10K-ohm pull up resistor to 3.3V.
How can Flash be used in an Embedded System?
For implementing flash memory on the ISA bus, please refer to AP-664 Designing Intel StrataFlash® Memory into Intel® Architecture.
For implementing flash memory on the PCI bus, please refer to AP-758 Flash Memory PCI Add-In Card for Embedded Systems. The Flash Memory PCI Add-In Card for Embedded Systems Schematics and Software Files is also available. |
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Intel® 440BX AGPset