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What are the major differences between the Intel® 845 Chipset and the Intel® 845E Chipset?
The two main differences are that 845 uses ICH2 and supports both SDR and DDR SDRAM memory, while 845E uses ICH4 and only supports DDR SDRAM memory.
Can the Intel 845E Chipset support PC133 SDR SDRAM if configured like the Intel 845 Chipset?
845E is a silicon spin of 845, removing SDR SDRAM support from the memory controller. With this change, PC133 memory should never work on an 845E chipset system, even if the hardware is properly strapped.
Is it possible to disable the LAN interface on the ICH2/ICH4?
The ICH2 has internal pull-ups, so if there is nothing connected to the integrated LAN device to any thing such as a CNR (Communication Network Riser) or the 82562 Platform LAN Connect (PLC) device, the integrated LAN gets disabled completely.
Can the ICH2 / ICH4 be used as a stand-alone controller, such as for the use of PCI, IDE, SMBus, or USB functions only?
This type of interface will not work. The Hublink interface is the most critical interface to the ICH2/ICH4. Without a connection to the GMCH and processor, the ICH2/ICH4 will never respond to any activity on either the PCI bus, IDE, SMBus, or USB. Intel recommends using a third-party solution for stand-alone support of these functions.
What is the PCI data queue size for the ICH2 and ICH4?
Both the ICH2 and ICH4 PCI interface have a 16 double-word data queue buffer for external PCI transactions. This aligns all transactions with the cache boundary size.
Why do all 845 and 845E Design Guides tie the SMBus to the System Management Link (SMLink) interface, and why are they isolated by FETs?
SMLink is an optional SMBus link for external system management ASIC or LAN controllers. Typically, SMBus is powered by the 3.3V power plane, while SMLink is powered by the 3.3V Standby power plane. Systems that implement standby voltages use the isolation to separate devices that can wake up a sleeping system from those that cannot.
For example, a LAN controller with Wake On LAN capabilities is isolated from a DIMM SPD that does not have such capability. Because of the FET separation, each power plane requires a pull-up resistor. If your system does not implement standby voltage, FET isolation is not necessary and SMLink can be connected directly with SMBus.
Does the ICH4 support simultaneous USB 1.1 & and USB 2.0 connections?
ICH4 was designed such that each port can operate at either USB 2.0 or USB 1.1, independent of what the other ports are operating at. The USB 2.0 480Mb/s bandwidth is per port and not a shared total. Each USB 2.0 port can operate at 480Mb/s.
What is "Virtual Wire Mode B", as mentioned in the ICH2 Specification Update, Specification Clarification 4?
Virtual Wire Mode B is a mode the ICH2 supports when using an external 8259A APIC in the system. If your system uses the internal xAPIC protocol and not an external 8259 APIC controller, then Specification Clarification 4 does not apply. |
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Intel® 845/845E Chipsets