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Note: Some of the links on this page will take you off the Intel web site. Intel does not control the content of the destination web site.
Manuals
Manuals for the Intel® 186 Embedded Processors are available on the Intel 186 Processor documentation site.
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I am using a 80C186XL and having difficulties getting the processor out of reset. It executes some code, then locks up.
You need to introduce hysteresis into the oscillator circuit. See the 80C186XL/80C188XL Embedded Processors Specification Update and the 80C186XL/80C188XL Reset Hysteresis Technical Note.
When writing to the reserve bits of the Intel 186/188 processor family, should the reserve bits be written to as a logic 0 or a logic 1?
The 80186/188 and 80C186/80C188 parts require writing ones to all reserved bit locations.
The 80C186XL/C188XL parts require writing zeros to all reserved bit locations. The 80C186Ex/188Ex parts require writing zeros to all reserved bit locations.
Failure to do so can cause sporadic operation. This is especially important when exporting code from the 80186/188 and 80C186/C188 to the standard 80C186XL/188XL or the enhanced 186 family (EA, EB, or EC). Intel does not guarantee operation of these processors with the reserved register bits at a logic one.
Math Co-Processor for the Intel 186 Processor family.
The math co-processors for the Intel 186/188 family of products have been End Of Lifed (EOLed) by Intel.
See End-Of-Life (EOL) notification #229; Title: (EOL) 80C187 Math Co-processor.
Last Date for Orders: 31-JAN-1997, Last Date for Shipments: 31-DEC-1997
Intel sends EOL notification to its distributors. Distributors are responsible for notification of their effected customers.
The Intel® 187 math co-processor is sole-sourced from Intel; there are no known product alternatives. Therefore, customers should not design with the 80C187. There are no hardware solutions for replacing the functions of the 187 math co-processor. Customers requiring floating point math should seek software solutions from third party software vendors.
Suggested upgrade path is to redesign using a Intel486™, 80486DX2 or DX4.
3rd Party Software:
Microway*
Research Park
Box 79
Kingston, MA 02364
Sales Department: 508-746-7341
URL: http://www.microway.com/index.html
NetUSA Software Center*
Mountain View, CA 94040
Phone: (415) 948-6200
Fax: (415) 948-6296
Sales : 1-800-628-DISK
Emulation Libraries
URL: http://www.simtel.net/pub/msdos/emulate/
387.zip — Software emulation of 80387 co-processor chip
87test.zip — Performs diagnostic check on math co-processor
chkcop22.zip — Math co-processor test utility from Intel Corp.
em87v1_3.zip — 8087 math co-processor emulator for AT or 386
emul87.zip — TSR emulates 8087 math processor (286/386 req)
mcpdiag.zip — Co-processor diagnostics utility from Intel
q87_402.zip — Q87 v4.02: Math Emulator for DOS, Win 3.x & 95
Quantasm Corporation*
19672 Stevens Creek Blvd
Suite #307
Cupertino, CA 95014
Phone: 408-244-6826
URL: http://www.quantasm.com/
Semiconductor Sources
California Digital, Inc.*
17700 Figueroa Street
Gardena, CA 90248
Telephone: (310) 217-0500
FAX: (310) 217-1951
URL: http://www.cadigital.com/semicond.htm
Intel 186 processor family history - 80C186 and 80C188.
Intel announced these second-generation CMOS products in 1987. These parts are no longer available; they have been replaced by the 80C186XL and 80C188XL.
The CHMOS III version is pin compatible while adding an enhanced feature set:
Upgrades:
– Runs at twice the clock rate of the NMOS 80186 and 80188
Upgrades:
– Consumes less than one-forth the power
See 80C186XL/ 80C188XL C-Step Compatibility with the 80C186.
Upgrades:
– The 80C186XL and 80C188XL are the direct upgrade for this part
– Pin compatible
– Timings: several timings have changed due to advantages in CMOS
– Reserve bit in all registers must be changed to a logic zero
Understanding interrupts on the Intel® 186 Processor Family.
AP-730 Interfacing the 82C59A to Intel® 186 Family Processors (Intel® Document #272822)
Many engineers have found that their applications require more external interrupt requests than are provided on the Intel 186 family of embedded processors. Intel® P82C59A-2 programmable interrupt controllers (PIC) can be added to a design to increase the number of available interrupt requests; this application note explains how. This application note contains the following:
– A reference design
– An analysis of the timings for the reference design and design considerations related to this timing data
– Design considerations for cascading 82C59As
– Source code for the programs used to test the reference design and design considerations.
See the Intel web site for Application Note Appendix A, Source Code
See the Intel web site for Application Note Appendix B, Source Code
AP-731 Understanding the Interrupt Control Unit of the Intel® 80C186EC/80C188EC Processor (Intel document #272823)
This application note contains:
– A step-by-step description of the interrupt processing sequence.
– A description of subtleties associated with programming 82C59A registers.
This application note is meant to be used in conjunction with the 80C186EC/80C188EC Microprocessor Users Manual. Refer to the Users Manual for a complete explanation of the operation of 82C59A registers.
See the Intel web site for Application Note Appendix A, Source Code
I2ICE 186 In-Circuit emulator.
EOL (End of Life) and EOS (end of Support)
This product has been EOLed by Intel. Intel no longer produces or sells this product and has not done so for several years.
The 80C186/188 was EOLed and replaced by 80C186XL/188XL. Is it pin for pin compatible?
The 80C186XL/188XL is a functional replacement for the 80C186/188. The change occurred for two reasons: The 80C186XL/188XL parts have a new, fully static, modular core capable of being operated down to 0 MHz, and the 1 micron process reduces minimum timings on some signals. Upgrade will result in higher performance and lower power consumption.
Note that in the 80C186/80C188 require writing logic ones to all reserved bit locations, but the XL, EA, EB, and EC versions require writing logic zeros to all reserved bit locations.
Does the Intel 186 Processor have internal ROM or RAM?
No. Memory must be interfaced externally. Our Intel® MCS® 51 and MCS® 96 microcontroller families have internal ROM and RAM available.
Will DMA latency occur during every transfer or just at the first?
Latency will happen every time a NEW transfer is called for by the requester. It does not happen between transfer in a block transfer. In a block transfer the entire block is transferred in back to back cycles with a most an idle state in between. When that transfer is finished and timer2 triggers a new transfer then latency will be involved for the first transfer of the block. If it is single transfers each time timer2 fires, latency will always be a factor. |
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Intel® 186/188 Processor
