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Note: The Intel® Pentium® III Processor - Low Power Module is discontinued. Technical documentation for the Low Power Modules has moved to the Embedded Intel® Architecture Archive Library.
Has the Intel® Pentium® III Low Power Module been discontinued?
Yes. The 500MHz Low Power Module (LPM) modules were discontinued with a last time order date of December 27, 2002.
What happened with the recent processor core change?
The 500MHz Pentium III LPM underwent a processor core stepping upgrade, going from a B-0 step Pentium III processor to a C-0 step Pentium III processor. Customer affect due to change is minimal.
Is the C-0 stepping of the Pentium III 500 MHz Low Power Module a drop in replacement for the B-0 and A-2 stepping?
The C-0 stepping of the LPM500 is pin for pin compatible with previous modules. However there are certain design considerations that must be taken into account. There are no electrical and thermal differences between the C-0 step and B-0 step modules. There are software considerations to be made, as described in PCN 102729.
Compared to A-2 modules, the B-0 and C-0 stepping of the LPM500 may require board level design changes as the requirements for BCLK have changed between the two steppings.
For B-0 and C-0 step processors:
Vih,BCLK Min spec is changed to 2.0V (from 1.7V for A2 step)
Vil,BCLK Max spec is changed to 0.5V (from 0.7V for A2 step). Due to this, new values are specified for BCLK high and low times for B- and C-00 step processors These changes were incorporated into the Mobile Intel® Pentium® III Processor in BGA2 and Micro-PGA2 Packages Datasheet.
What kind of SDRAM clock buffer should I use with the 440BX?
Zero delay clock buffers have internal PLLs which cause contention with the PLL internal to the 440BX. This contention can be observed in the form of jitter on the 440BX DCLKO and DCLKWR signals. As another observable symptom the system will lockup after the processor attempts to fetch the first 8 bytes of BIOS. The customer should use SDRAM clock buffers that do not have an internal PLL.
Are 256Mbit SDRAM's supported?
The 82443BX does not support 256Mbit technology SDRAM.
128Mbit technology SDRAM using 16MX8 devices has been tested in the Intel® 82440BX System Validation (SV) platform using the 82443BX C-1 stepping. This SDRAM memory configuration was double-sided. Each SDRAM DIMM module therefore contained a total of 256Mb of memory. A total of four DIMM modules were available for testing. For further information please see page 25 of the specification update.
There were no detection or sizing problems with this SDRAM memory array using the 82440BX SV board and 82440BX SV BIOS. The 82440BX AGPset supports the use of 128Mbit technology SDRAM memory using the 82443BX C-1 stepping as described in this paragraph.
It is recommended that OEMs wishing to use 128Mbit technology SDRAM perform validation using their own BIOS on their own 82440BX AGPset systems.
What BIOS changes need to be made in order to support the change in PID bits indicated in PCN 1056?
The system BIOS may need modification if the PID bits are not checked prior to applying a microcode update patch. In addition, the BIOS may need to incorporate the latest microcode update for the new processor. Microcode update patches can be obtained through your Intel Field Representative.
The PID bits are stored in the CPU's MSR: BBL_CR_OVRD (0x17h).
For additional information, please refer to the following documentation:
Intel® Architecture Software Developer's Manual Volume 3: System Programming (Section 8.10) and PCN 1056. |
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Intel® Pentium® III Processor - Low Power Module