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Preventing Transmit FIFO Underflows
To prevent IXF1002 Transmit FIFO underflows, applications should be designed with the highest possible IX Bus frequency, thus utilizing maximum IX Bus bandwidth. Additional Transmit underflow prevention can be obtained by increasing the value of the Transmit Threshold register (TX_TSHD) to a level that maintains adequate data in the FIFO.
(GCIXF1002EC) Txrdy Stops Asserting
Txrdy of a port, will stop asserting when the transmit FIFO is full or when two packets are present in the FIFO. The maximum number of packets in the (–EC version) IXF1002 transmit FIFO is two. You can determine the number of packets in the transmit FIFO by reading the IXF1002 CSR register TX_RX_STT(PKC). Packet transmission starts when EOP enters the transmit FIFO or when the packet threshold TX_TSHD(TSD) is met. For packet sizes greater than 64 Bytes, you may realize additional transmit efficiency by lowering the transmit threshold TX_TSHD(TSD).
The latest version of the IXF1002, part number GCIXF1002ED, enhances performance by allowing up to 16 packets in the TX FIFO. The –ED version part number GCIXF1002ED can be used as a direct replacement for the –EC device.
Large Frame Support
The IXF1002 supports large frames (Jumbo Packets) up to 64K Bytes. The maximum packets size is programmed by writing to the Max packet size register PKT_MAX_SIZE. It is possible to receive frames larger than the PKT_MAX_SIZE by programming the TX_RX_ERR(PRTL) to “pass too long packets”. There are no limitations on the Transmit frame size.
Failure to Establish Link (GPCS Mode)
During the initialization of the IXF1002 port mode from GMII (reset value) to GPCS mode (PORT_MODE(GPCS) ), the IXF1002 sets the remote fault bit AN_ADV(RF). Some Link partners may fail to establish link while the IXF1002 advertises remote fault AN_ADV(RF). To obtain Link, driver software should be written to clear the remote fault AN_ADV(RF), reset the GPCS GMII_CTL(RST) and restart Auto-negotiation GMII_CTL(RESAN).
IXF1002 Reference Design
For IXF1002 reference designs, customers can refer to the IXP1200 Evaluation Board. The IXP1200 Evaluation Board Reference design implements the IXF1002 Dual Gigabit Mac with the Agilent* HDMP-1636A SerDes transceiver.
IXF1002 Verilog Models for Simulation
To improve time to market and minimize redesign activities, customers designing ASIC/FPGA interfaces to the IXF1002 are encouraged to use the Verilog model simulation. Simulation Models are available for the IXF1002 in Model Tech MTI, VCS and Verilog XL formats. To obtain the simulation models, please contact your local Intel Sales or Distributor representative.
Programming the CPU Interface 16-bit Mode
The IXF1002 supports two CPU bus widths: 8-bit(default) and 16-bit (controlled by the PORT_MODE(CPUBW) bit). To enable 16-bit CPU width operation the PORT_MODE register must first be accessed in 8-bit mode to set the PORT_MODE(CPUBW) bit. Once set (PORT_MODE(CPUBW)) all following CSR register access will be in 16-bit mode.
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Intel® IXF1002 Dual-Port Gigabit Ethernet MAC