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Intel® Server Board SE7525GP2
Memory Controller Hub Interrupt Message Re-Ordering Across Hub Interface [PDF]

Technical Advisory: 703-01 Intel® E7525 MCH Interrupt Message Re-Ordering across Hub Interface Erratum: Impact to Intel® Server Board SE7525GP2.

An erratum affecting PCI Express* slot capabilities has been found in the Intel® E7525 server chipset during testing and is root caused. Please reference Intel® E7525 MCH Specification Update Erratum #24: "Interrupt Message Re-Ordering across Hub Interface Erratum" for a complete description of the MCH errata. The Intel® Server Board SE7525GP2 is affected by this erratum.

Intel Server Board SE7525GP2 based systems running with a single processor thread and operating in legacy PIC mode or virtual wire Mode A may hang under high I/O-driver interrupt stress. For systems operating in full APIC mode where the number of virtual interrupt line (intA, intB, etc.) used by all PCI-Express adapters in a system exceeds the number of logical processors (threads), the system may hang.



icon  Technical Advisory 703-01 [PDF]
File Name: ta7031se7525gp2mch.pdf
Size: 25,461 bytes
Date: July 2004
File Revision: TA-703-1

Note: PDF Files require Adobe Acrobat* Reader



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This applies to:
Intel® Server Board SE7525GP2



Solution ID: CS-013933
Date Created: 28-Jul-2004
Last Modified: 26-Sep-2005
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