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Intel has confirmed the possibility of compressed clock signals on the chipset downstream IMB bus between the Serverworks Serverset III HE*, "CIOB" and "HE" ASICs, causing a resulting timing margin loss relative to the data signal in the downstream direction. Intel's investigation indicates that due to the intermittent nature of the issue, manufacturing tests may not have screened this issue completely and therefore some exposure in the installed base is probable on all 751519-5xx, and 751519-603 baseboards.
The margin loss caused by the compressed IMB clock signals could potentially cause incorrect data transfer at the CIOB resulting in an undetected disk write error or other undetected PCI write error.
For more information, please refer to the Technical Advisory below.
TA_0414.PDF
Size: 101530 bytes
Date: 10/28/2002 1:32:00 PM
Note: PDF Files require Adobe Acrobat* Reader†
† This link will take you off of the Intel Web site. Intel does not control the content of the destination Web Site.
This applies to:
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