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This document clarifies how the Pentium® Pro processor handles processor accesses to Write Protect (WP) memory.
The Pentium Pro Family Developer's Manual, Volume 1, Page 7-2, "Memory Types: WB, WT, WP and UC", states that, "...a WP hit to the L2 cache invalidates the line in the L2 cache." There is no mention of L1 cache. Please clarify if there is a valid copy of the line in L1 and L2, does it invalidate both copies?
According to the Pentium Pro processor bus specification, WP memory is treated as Write Through (WT) memory on reads, and uncacheable (UC) memory on writes. Therefore, on a write to WP memory, which is treated as a write to UC memory, the write will go directly to the bus, passing any copies in the L1 and L2 caches. If there are valid copies (i.e.; in the S-state, since WP memory only supports S or I states) of that line in either L1 or L2, it will be invalidated.
This applies to:
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