Intel® Developer Network for PCI Express* Architecture
Resources
Specifications
PHY Interface for the PCI Express* (PIPE) Architecture Gen 2 Revision 2.0(PDF 243KB)
This document is a final version of the PIPE spec that supports PCI Express* Gen 2. The PIPE spec (PHY Interface for PCI Express* Architecture) describes a standardized interface between PCIe MAC implementations and PCIe PHY implementations. This document can be used for both discrete PHY parts and for PHYs that are foundry macrocell implementations. Comments can be sent to daniel.s.froelich@intel.com.
MAC-PHY Interface Connector for PCI Express* (PIPE) Architecture(PDF 397KB)
August 19, 2005
This document describes a standardized connector interface for discrete PHYs. The connector can handle PHYs with up to four lanes. The design is intended for prototyping/testing work, allowing MAC developers to be able to easily connect to PHYs from different vendors, and similarly provide an easy way for PHY vendors to try their designs with multiple MAC vendors.
PHY Interface for the PCI Express* Rev. 1.1 (PIPE) Architecture(PDF 373KB)
June 16, 2003
This document describes a standardized interface between PCIe MAC implementations and PCIe PHY implementations. This document can be used for both discrete PHY parts and for PHYs that are foundry macrocell implementations.
